参考文献

[1] BRIER E, CLAVIER C, OLIVIER F. Correlation power analysis with a leakage model[C]//Proceedings of the Cryptographic Hardware and Embedded Systems（CHES）.[S.l.]: Springer Berlin Heidelberg, 2004:16-29.

[2] ORS S B, GURKAYNAK F, OSWALD E, et al. Power-analysis attack on an asicaes implementation[C]// Proceedings of the International Conference on Information Technology: Coding and Computing.[S.l.]: IEEE, 2004:546-552.

[3] KOCHER P, JAFFE J, JUN B. Differential power analysis[C]//Proceedings of the Advances in Cryptology-CRYPTO’99.[S.l.]: Springer, 1999:789-789.

[4] GUILLEY S, HOOGVORST P, PACALET R. Differential power analysis model and some results[M]// QUISQUATER J J, PARADINAS P, DESWARTE Y, et al. Smart Card Research and Advanced Applications VI: volume 153.[S.l.]: Springer US, 2004:127-142.

[5] PEETERS E, STANDAERT F X, QUISQUATER J J. Power and electromagnetic analysis: Improved model, consequences and comparisons[J]. Integration the VLSI Journal, 2007,40（1）: 52-60.

[6] STANDAERT F X, MACE F, PEETERS E, et al. Updates on the security of fpgas against power analysis attacks[C]//Proceedings of the International Workshop on Applied Reconfigurable Computing.[S.l.]: Springer Berlin Heidelberg, 2006:335-346.

[7] MARTINASEK Z, ZEMAN V, TRASY K. Simple electromagnetic analysis in cryptography[J]. International Journal of Advances in Telecommunications, 2012,1（1）: 13-19.

[8] BADRIGNANS B, DANGER J L, FISCHER V, et al. Security trends for fpgas: From secured to secure reconfigurable systems[M].[S.l.]: Springer Science & Business Media, 2011.

[9] MANGARD S. A simple power-analysis（spa）attack on implementations of the aes key expansion[C]// Proceedings of the International Conference on Information Security and Cryptology.[S.l.]: Springer, 2002:343-358.

[10] MARTINASEK Z, CLUPEK V, KRISZTINA T. General scheme of differential power analysis[C]// Proceedings of the International Conference on Telecommunications and Signal Processing.[S.l.]: IEEE, 2013:358-362.

[11] MANGARD S, OSWALD E, POPP T. Power analysis attacks: Revealing the secrets of smart cards（advances in information security）[M]. New York, USA: Springer, 2007.

[12] RATHNALA P, WILMSHURST T, KHARAZ A. A practical approach to differential power analysis using pic micrcontroller based embedded system[C]//Proceedings of the Computer Science and Electronic Engineering Conference.[S.l.]: IEEE, 2014:58-62.

[13] MASOOMI M, MASOUMI M, AHMADIAN M. A practical differential power analysis attack against an fpga implementation of aes cryptosystem[C]//Proceedings of the International Conference on Information Society.[S.l.]: IEEE, 2010:308-312.

[14] PETRVALSKY M, DRUTAROVSKY M, VARCHOLA M. Differential power analysis of advanced encryption standard on accelerated 8051 processor[C]//Proceedings of the 23rd International Conference Radioelektronika（RADIOELEKTRONIKA）.[S.l.]: IEEE, 2013:334-339.

[15] BENESTY J, CHEN J, HUANG Y, et al. Pearson correlation coefficient[M].[S.l.]: Springer Berlin Heidelberg, 2009:37-40.

[16] KOCHER P. Timing attacks on implementations of diffie-hellman, rsa, dss, and other systems[C]//Lecture Notes in Computer Science: volume 1109 Proceedings of the Advances in Cryptology（CRYPTO’96）.[S.l.]: Springer, 1996:104-113.

[17] DHEM J F, KOEUNE F, LEROUX P A, et al. A practical implementation of the timing attack[C]// Proceedings of the International Conference on Smart Card Research and Advanced Applications.[S.l.]: Springer, 1998:167-182.

[18] SONG D X, WAGNER D, TIAN X. Timing analysis of keystrokes and timing attacks on ssh[C]//Proceedings of the Conference on USENIX Security Symposium.[S.l.]: USENIX Association, 2001:1-16.

[19] TOTH R, FAIGL Z, SZALAY M, et al. An advanced timing attack scheme on rsa[C]//Proceedings of the International Telecommunications Network Strategy and Planning Symposium.[S.l.]: IEEE, 2008:1-24.

[20] MONTGOMERY P L. Modular multiplication without trial division[J]. Mathematics of Computation, 1985,44（170）: 519-521.

[21] CANVEL B, HILTGEN A, VAUDENAY S, et al. Password interception in a ssl/tls channel[J]. Information Technology Journal, 2004,3（3）: 583-599.

[22] KUNE D F, KIM Y. Timing attacks on pin input devices[C]//Proceedings of the ACM Conference on Computer and Communications Security.[S.l.]: ACM, 2010:678-680.

[23] CAGALJ M, PERKOVIC T, BUGARIC M. Timing attacks on cognitive authentication schemes[J]. IEEE Transactions on Information Forensics & Security, 2015,10（3）: 584-596.

[24] J. S S, A. M, P. E. Differential power analysis（dpa）attack on dual field ecc processor for cryptographic applications[C]//Proceedings of the International Conference on Computer Communication and Informatics.[S.l.]: IEEE, 2014:1-5.

[25] GUO L, WANG L, LI Q, et al. Differential power analysis on dynamic password token based on sm3 algorithm, and countermeasures[C]//Proceedings of the International Conference on Computational Intelligence and Security.[S.l.]: IEEE, 2016:354-357.

[26] TANG S, WU L, ZHANG X, et al. A novel method of correlation power analysis on sm4 hardware implementation[C]//Proceedings of the 12th International Conference on Computational Intelligence and Security.[S.l.]: IEEE, 2017:203-207.

[27] DUAN X, CUI Q, WANG S, et al. Differential power analysis attack and efficient countermeasures on present[C]//Proceedings of the IEEE International Conference on Communication Software and Networks.[S.l.]: IEEE, 2016:8-12.

[28] LI H, WU K, PENG B, et al. Enhanced correlation power analysis attack on smart card[C]//Proceedings of the 9th International Conference for Young Computer Scientists.[S.l.]: IEEE, 2008:2143-2148.

[29] SOCHA P, BREJNIK J, BARTIK M. Attacking aes implementations using correlation power analysis on zybo zynq-7000 soc board[C]//Proceedings of the 7th Mediterranean Conference on Embedded Computing（MECO）.[S.l.]: IEEE, 2018:1-4.

[30] VAN WOUDENBERG J G J, WITTEMAN M F, BAKKER B. Improving differential power analysis by elastic alignment[C]//Proceedings of the International Conference on Topics in Cryptology（CT-RSA）.[S.l.]: Springer, 2011:104-119.

[31] PATEL H, BALDWIN R. Differential power analysis using wavelet decomposition[C]//Proceedings of the IEEE Military Communications Conference（MILCOM）.[S.l.]: IEEE, 2012:1-5.

[32] FENG M, ZHOU Y, YU Z. Emd-based denoising for side-channel attacks and relationships between the noises extracted with different denoising methods[C]//Proceedings of the International Conference on Information and Communications Security.[S.l.]: Springer, 2013:259-274.

[33] LI J, LI S, SHI Y, et al. Wavelet de-noising method in the side-channel attack[C]//Proceedings of the IEEE International Conference on Signal Processing, Communications and Computing.[S.l.]: IEEE, 2015:1-5.

[34] AI J, WANG Z, ZHOU X, et al. Improved wavelet transform for noise reduction in power analysis attacks[C]//Proceedings of the IEEE International Conference on Signal and Image Processing.[S.l.]: IEEE, 2017:602-606.

[35] AI J, WANG Z, ZHOU X, et al. Variational mode decomposition based denoising in side channel attacks[C]//Proceedings of the IEEE International Conference on Computer and Communications.[S.l.]: IEEE, 2017:1683-1687.

[36] HUANG N E, SHEN Z, LONG S R, et al. The empirical mode decomposition and the hilbert spectrum for nonlinear and non-stationary time series analysis[J]. Proceedings Mathematical Physical & Engineering Sciences, 1998,454（1971）: 903-995.

[37] SWAMY T, SHAH N, LUO P, et al. Scalable and efficient implementation of correlation power analysis using graphics processing units（gpus）[C]//Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy.[S.l.]: ACM, 2014:1-8.

[38] GAMAARACHCHI H, RAGEL R, JAYASINGHE D. Accelerating correlation power analysis using graphics processing units（gpus）[C]//Proceedings of the International Conference on Information and Automation for Sustainability.[S.l.]: IEEE, 2014:1-6.

[39] PAMMU A A, CHONG K S, LWIN N K Z, et al. Success rate model for fully aes-128 in correlation power analysis[C]//Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems（APCCAS）.[S.l.]: IEEE, 2017:115-118.

[40] MAZUR L, NOVOTNY M. Differential power analysis on fpga board: Boundaries of success[C]// Proceedings of the 6th Mediterranean Conference on Embedded Computing（MECO）.[S.l.]: IEEE, 2017:1-4.

[41] RECHBERGER C, OSWALD E. Practical template attacks[M].[S.l.]: Springer, 2004:440-456.

[42] OU C, WANG Z, SUN D, et al. A new efficient interesting points enhanced electromagnetic attack on at89s52[C]//Proceedings of the IEEE International Symposium on Electromagnetic Compatibility.[S.l.]: IEEE, 2016:176-181.

[43] MEYNARD O, REAL D, FLAMENT F, et al. Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques[C]//Proceedings of the Design, Automation & Test in Europe Conference & Exhibition.[S.l.]: IEEE, 2011:1004-1009.

[44] MAURINE P, PERIN G, TORRES L, et al. Amplitude demodulation-based em analysis of different rsa implementations[C]//Proceedings of the Design, Automation & Test in Europe Conference & Exhibition（DATE）.[S.l.]: IEEE, 2012:1167-1172.

[45] ZHOU X, SUN D, WANG Z, et al. An adaptive singular value decomposition-based method to enhance cor-relation electromagnetic analysis[C]//Proceedings of the IEEE International Symposium on Electromagnetic Compatibility.[S.l.]: IEEE, 2016:170-175.

[46] DENIS, VALETTE, FR, et al. Enhancing correlation electromagnetic attack using planar near-field cartography[C]//Proceedings of the Design Automation & Test in Europe（DATE）.[S.l.]: IEEE, 2010:628-633.

[47] DEHBAOUI A, LOMNE V, MAURINE P, et al. Enhancing electromagnetic attacks using spectral coherence based cartography[C]//Proceedings of the IFIP International Conference on Very Large Scale Integration.[S.l.]: Springer, 2009:11-16.

[48] DEHBAOUI A, LOMNE V, ORDAS T, et al. Enhancing electromagnetic analysis using magnitude squared incoherence[J]. IEEE Transactions on Very Large Scale Integration（VLSI）Systems, 2012,20（3）: 573-577.

[49] HEYSZL J, MANGARD S, HEINZ B, et al. Localized electromagnetic analysis of cryptographic implementations[C]//Proceedings of the Cryptographers Track at the RSA Conference.[S.l.]: Springer, 2012:231-244.

[50] WITTKE C, DYKA Z, LANGENDOERFER P. Comparison of em probes using sema of an ecc design[C]//Proceedings of the IFIP International Conference on New Technologies, Mobility and Security.[S.l.]: Springer, 2016:1-5.

[51] KUMAR A, SCARBOROUGH C, YILMAZ A, et al. Efficient simulation of em side-channel attack resilience[C]//2017 IEEE/ACM International Conference on Computer-Aided Design（ICCAD）.[S.l.]: IEEE, 2017:123-130.

[52] LI Y, MENG X, WANG S, et al. Weighted key enumeration for em-based side-channel attacks[C]// Proceedings of the IEEE International Symposium on Electromagnetic Compatibility and IEEE Asia-Pacific Symposium on Electromagnetic Compatibility（EMC/APEMC）.[S.l.]: IEEE, 2018:749-752.

[53] MARTIN D P, OCONNELL J F, OSWALD E, et al. Counting keys in parallel after a side channel attack[C]//Proceedings of the Advances in Cryptology ASIACRYPT.[S.l.]: Springer Berlin Heidelberg, 2015:313-337.

[54] VEYRATCHARVILLON N, GERARD B, STANDAERT F. Security evaluations beyond computing power[C]//Proceedings of the Advances in Cryptology EUROCRYPT.[S.l.]: Springer, 2013:126-141.

[55] HEYSZL J, MERLI D, HEINZ B, et al. Strengths and limitations of high-resolution electromagnetic field measurements for side-channel analysis[C]//Proceedings of the International Conference on Smart Card Research and Advanced Applications.[S.l.]: Springer, 2012:248-262.

[56] SPECHT R, HEYSZL J, SIGL G. Investigating measurement methods for high-resolution electromagnetic field side-channel analysis[C]//Proceedings of the International Symposium on Integrated Circuits.[S.l.]: IEEE, 2015:21-24.

[57] KIZHVATOV I. Analysis and improvement of the random delay countermeasure of ches 2009[C]// Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2010:95-109.

[58] MATEOS E, GEBOTYS C H. A new correlation frequency analysis of the side channel[C]//Proceedings of the 5th Workshop on Embedded Systems Security（WESS）.[S.l.]: ACM, 2010:1-8.

[59] WANG Z, ZHOU X, DEBRUNNER V, et al. Hirschman optimal transform based correlation frequency electromagnetic analysis[C]//Proceedings of the IEEE International Symposium on Electromagnetic Com-patibility（EMC）.[S.l.]: IEEE, 2016:144-147.

[60] YOSHIKAWA M, NOZAKI Y. Electromagnetic analysis method for ultra low power cipher midori[C]// Proceedings of the IEEE Ubiquitous Computing, Electronics and Mobile Communication Conference.[S.l.]: IEEE, 2017:70-75.

[61] KABIN I, DYKA Z, DAN K, et al. Horizontal address-bit dema against ecdsa[C]//Proceedings of the IFIP International Conference on New Technologies, Mobility and Security.[S.l.]: Springer, 2018:1-7.

[62] ITOH K, IZU T, TAKENAKA M. Address-bit differential power analysis of cryptographic schemes ok-ecdh and ok-ecdsa[C]//Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2002:129-143.

[63] ASONOV D, AGRAWAL R. Keyboard acoustic emanations[C]//Proceedings of the IEEE Symposium on Security and Privacy.[S.l.]: IEEE, 2004:3-11.

[64] LI Z, FENG Z, TYGAR J D. Keyboard acoustic emanations revisited[C]//Proceedings of the ACM Conference on Computer and Communications Security（CCS）. Alexandria, VA, USA: ACM, 2005:373-382.

[65] FARUQUE M A A, CHHETRI S R, CANEDO A, et al. Acoustic side-channel attacks on additive manufacturing systems[C]//Proceedings of the ACM/IEEE 7th International Conference on Cyber-Physical Systems（ICCPS）.[S.l.]: IEEE, 2016:1-10.

[66] CHHETRI S R, CANEDO A, FARUQUE M A A. Confidentiality breach through acoustic side-channel in cyber-physical additive manufacturing systems[J]. ACM Transactions on Cyber-Physical Systems, 2017,2（1）: 1-25.

[67] BACKES M, DURMUTH M, GERLING S, et al. Acoustic side-channel attacks on printers[C]//Proceedings of the USENIX Security symposium.[S.l.]: USENIX Association, 2010:307-322.

[68] MARTINASEK Z, CLUPEK V, TRASY K. Acoustic attack on keyboard using spectrogram and neural network[C]//Proceedings of the International Conference on Telecommunications and Signal Processing.[S.l.]: IEEE, 2015:637-641.

[69] MAIMUN, ROSMANSYAH Y. The microphone array sensor attack on keyboard acoustic emanations: Side-channel attack[C]//Proceedings of the International Conference on Information Technology Systems and Innovation.[S.l.]: IEEE, 2017:261-266.

[70] TOREINI E, RANDELL B, HAO F. An acoustic side channel attack on enigma[R]. School of Computing Science, University of Newcastle upon Tyne, 2015.

[71] CHHETRI S R, FAEZI S, FARUQUE M A A. Information leakage-aware computer-aided cyber-physical manufacturing[J]. IEEE Transactions on Information Forensics & Security, 2018,13（9）: 2333-2344.

[72] STELLARI F, ZAPPA F, COVA S, et al. Tools for non-invasive optical characterization of cmos circuits[C]// Proceedings of the International Electron Devices Meeting（IEDM）. Technical Digest.[S.l.]: IEEE, 1998:487-490.

[73] FERRIGNO J, HLAVAC M. When aes blinks: introducing optical side channel[J]. IET Information Security, 2008,2（3）: 94-98.

[74] SKOROBOGATOV S. Using optical emission analysis for estimating contribution to power analysis[C]// Proceedings of the Workshop on Fault Diagnosis and Tolerance in Cryptography（FDTC）.[S.l.]: IEEE, 2009:111-119.

[75] SHAHRJERDI D, RAJENDRAN J, GARG S, et al. Shielding and securing integrated circuits with sensors[C]//Proceedings of the IEEE/ACM International Conference on Computer-Aided Design.[S.l.]: IEEE, 2014:170-174.

[76] BROUCHIER J, KEAN T, MARSH C, et al. Temperature attacks[J]. IEEE Security Privacy, 2009,7（2）: 79-82.

[77] IAKYMCHUK T, NIKODEM M, KPA K. Temperature-based covert channel in fpga systems[C]//Proceedings of the International Workshop on Reconfigurable Communication-Centric Systems-On-Chip.[S.l.]: IEEE, 2011:1-7.

[78] MASTI R J, RAI D, RANGANATHAN A, et al. Thermal covert channels on multi-core platforms[C]// Proceedings of the USENIX Security Synposium.[S.l.]: USENIX Association, 2015:865-880.

[79] AMROUCH H, KRISHNAMURTHY P, PATEL N, et al. Emerging（un-）reliability based security threats and mitigations for embedded systems: speical session[C]//Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems.[S.l.]: ACM, 2017:1-10.

[80] PENG G, STOW D, BARNES R, et al. Thermal-aware 3d design for side-channel information leakage[C]//Proceedings of the IEEE International Conference on Computer Design.[S.l.]: IEEE, 2016:520-527.

[81] KNECHTEL J, SINANOGLU O. On mitigation of side-channel attacks in 3d ics: Decorrelating thermal patterns from power and activity[C]//Proceedings of the 54th Design Automation Conference.[S.l.]: IEEE, 2017:1-6.

[82] DAN B, DEMILLO R A, LIPTON R J. On the importance of checking cryptographic protocols for faults[C]//Proceedings of the International Conference on Theory and Application of Cryptographic Techniques.[S.l.]: Springer, 1997:37-51.

[83] BIHAM E, SHAMIR A. Differential fault analysis of secret key cryptosystems[C]//Proceedings of the Advances in Cryptology CRYPTO.[S.l.]: Springer, 1997:513-525.

[84] FAN J, GIERLICHS B, VERCAUTEREN F. To infinity and beyond: Combined attack on ecc using points of low order[C]//Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2012:143-159.

[85] CLAVIER C, FEIX B, GAGNEROT G, et al. Passive and active combined attacks on aes combining fault attacks and side channel analysis[C]//Proceedings of the Fault Diagnosis and Tolerance in Cryptography.[S.l.]: Springer, 2010:10-19.

[86] DASSANE F, VENELLI A. Combined fault and side-channel attacks on the aes key schedule[C]//Proceedings of the Workshop on Fault Diagnosis and Tolerance in Cryptography.[S.l.]: IEEE, 2012:63-71.

[87] BARENGHI A, HOCQUET C, BOL D, et al. Exploring the feasibility of low cost fault injection attacks on sub-threshold devices through an example of a 65nm aes implementation[C]//Proceedings of the International Workshop on Radio Frequency Identification: Security and Privacy Issues.[S.l.]: Springer Berlin Heidelberg, 2012:48-60.

[88] AMIEL F, CLAVIER C, TUNSTALL M. Fault analysis of dpa-resistant algorithms[C]//Proceedings of the International Conference on Fault Diagnosis and Tolerance in Cryptography.[S.l.]: Springer, 2006:223-236.

[89] DUMONT M, LISART M, MAURINE P. Modeling and simulating electromagnetic fault injection[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020.

[90] SKOROBOGATOV S P, ANDERSON R J. Optical fault induction attacks[C]//Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2002:2-12.

[91] BARENGHI A, BREVEGLIERI L, KOREN I, et al. Fault injection attacks on cryptographic devices: Theory, practice, and countermeasures[J]. Proceedings of the IEEE, 2012,100（11）: 3056-3076.

[92] SAHA D, MUKHOPADHYAY D, CHOWDHURY D R. A diagonal fault attack on the advanced encryption standard[R]. Cryptology ePrint Archive, 2009.

[93] DEHBAOUI A, DUTERTRE J M, ROBISSON B, et al. Injection of transient faults using electromagnetic pulses practical results on a cryptographic system[R]. Cryptology ePrint Archive, 2012.

[94] ROMAILLER Y, PELISSIER S. Practical fault attack against the ed25519 and eddsa signature schemes[C]// Proceedings of the Workshop on Fault Diagnosis & Tolerance in Cryptography.[S.l.]: Springer, 2017:17-24.

[95] AMIEL F, VILLEGAS K, FEIX B, et al. Passive and active combined attacks: Combining fault attacks and side channel analysis[C]//Proceedings of the Workshop on Fault Diagnosis and Tolerance in Cryptography（FDTC）.[S.l.]: Springer, 2007:92-102.

[96] PATRANABIS S, BREIER J, MUKHOPADHYAY D, et al. One plus one is more than two: A practical combination of power and fault analysis attacks on present and present-like block ciphers[C]//Proceedings of the Workshop on Fault Diagnosis & Tolerance in Cryptography.[S.l.]: Springer, 2017:25-32.

[97] LI Y, OHTA K, SAKIYAMA K. New fault-based side-channel attack using fault sensitivity.[J]. IEEE Transactions on Information Forensics & Security, 2012,7（1）: 88-97.

[98] KELSEY J, SCHNEIER B, WAGNER D, et al. Side channel cryptanalysis of product ciphers[C]//Proceedings of the European Symposium on Research in Computer Security.[S.l.]: Springer, 1998:97-110.

[99] PAGE D. Theoretical use of cache memory as a cryptanalytic side-channel[R]. Cryptology ePrint Archive, 2002.

[100] NEVE M, SEIFERT J P, WANG Z. A refined look at bernstein's aes side-channel analysis[C]//Proceedings of the ACM Symposium on Information, Computer and Communications Security.[S.l.]: ACM, 2006:369-369.

[101] REBEIRO C, MUKHOPADHYAY D. Boosting profiled cache timing attacks with a priori analysis[J]. IEEE Transactions on Information Forensics & Security, 2012,7（6）: 1900-1905.

[102] BHATTACHARYA S, REBEIRO C, MUKHOPADHYAY D. Hardware prefetchers leak: A revisit of svf for cache-timing attacks[C]//Proceedings of the IEEE/ACM International Symposium on Microarchitecture Workshops.[S.l.]: IEEE, 2012:17-23.

[103] GULLASCH D, BANGERTER E, KRENN S. Cache games -bringing access-based cache attacks on aes to practice[C]//Proceedings of the IEEE Symposium on Security and Privacy.[S.l.]: IEEE, 2011:490-505.

[104] YAROM Y, FALKNER K. Flush+reload: A high resolution, low noise, l3 cache side-channel attack[C]// Proceedings of the USENIX Conference on Security Symposium.[S.l.]: USENIX Association, 2014:719-732.

[105] TANG Y, LI H, XU G. Cache side-channel attack to recover plaintext against datagram tls[C]//Proceedings of the International Conference on IT Convergence and Security（ICITCS）.[S.l.]: IEEE, 2015:1-6.

[106] OSVIK D A, SHAMIR A, TROMER E. Cache attacks and countermeasures: The case of aes[C]//Proceedings of the Cryptographers Track at the RSA Conference.[S.l.]: Springer, 2006:1-20.

[107] LIU F, YAROM Y, GE Q, et al. Last-level cache side-channel attacks are practical[C]//Proceedings of the IEEE Symposium on Security and Privacy.[S.l.]: IEEE, 2015:605-622.

[108] KAYAALP M, ABU-GHAZALEH N, PONOMAREV D, et al. A high-resolution side-channel attack on last-level cache[C]//Proceedings of the Design Automation Conference.[S.l.]: ACM, 2016:72.

[109] YOUNIS Y A, KIFAYAT K, SHI Q, et al. A new prime and probe cache side-channel attack for cloud computing[C]//Proceedings of the IEEE International Conference on Computer and Information Technology; Ubiquitous Computing and Communications; Dependable, Autonomic and Secure Computing; Pervasive Intelligence and Computing.[S.l.]: IEEE, 2015:1718-1724.

[110] REINBRECHT C, SUSIN A, BOSSUET L, et al. Side channel attack on noc-based mpsocs are practical: Noc prime+probe attack[C]//Proceedings of the Symposium on Integrated Circuits and Systems Design: Chip on the Mountains.[S.l.]: IEEE, 2016:1-6.

[111] BUCCI M, GUGLIELMO M, LUZZI R, et al. A power consumption randomization countermeasure for dpa-resistant cryptographic processors[C]//Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation.[S.l.]: Springer Berlin Heidelberg, 2004:481-490.

[112] BUCCI M, LUZZI R, GUGLIELMO M, et al. A countermeasure against differential power analysis based on random delay insertion[C]//Proceedings of the IEEE International Symposium on Circuits and Systems.[S.l.]: IEEE, 2005:3547-3550.

[113] TIRI K, VERBAUWHEDE I. A logic level design methodology for a secure dpa resistant asic or fpga implementation[C]//Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.[S.l.]: IEEE, 2004:246-251.

[114] TIRI K, AKMAL M, VERBAUWHEDE I. A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards[C]//Proceedings of the 28th European Solid-State Circuits Conference.[S.l.]: IEEE, 2002:403-406.

[115] BUCCI M, GIANCANE L, LUZZI R, et al. Delay-based dual-rail precharge logic[J]. IEEE Transactions on Very Large Scale Integration Systems, 2011,19（7）: 1147-1153.

[116] MENICOCCI R, TRIFILETTI A, TROTTA F. A logic level countermeasure against cpa side channel attacks on aes[C]//Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems（MIXDES）.[S.l.]: IEEE, 2013:403-407.

[117] BELLIZIA D, BONGIOVANNI S, MONSURR P, et al. Secure double rate registers as an rtl countermeasure against power analysis attacks[J]. IEEE Transactions on Very Large Scale Integration Systems, 2018,26（7）: 1368-1376.

[118] LEVI I, KEREN O, FISH A. Data-dependent delays as a barrier against power attacks[J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2015,62（8）: 2069-2078.

[119] AVITAL M, DAGAN H, KEREN O, et al. Randomized multitopology logic against differential power analysis[J]. IEEE Transactions on Very Large Scale Integration（VLSI）Systems, 2015,23（4）: 702-711.

[120] AVITAL M, LEVI I, KEREN O, et al. Cmos based gates for blurring power information[J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2017,63（7）: 1033-1042.

[121] BUCCI M, GIANCANE L, LUZZI R, et al. Three-phase dual-rail pre-charge logic[C]//Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2006:232-241.

[122] CHARI S, JUTLA C S, RAO J R, et al. Towards sound approaches to counteract power-analysis attacks[C]//Proceedings of the International Cryptology Conference on Advances in Cryptology.[S.l.]: Springer, 1999:398-412.

[123] FUMAROLI G, MARTINELLI A, PROUFF E, et al. Affine masking against higher-order side channel analysis[C]//Proceedings of the International Conference on Selected Areas in Cryptography.[S.l.]: Springer, 2010:262-280.

[124] POPP T, KIRSCHBAUM M, ZEFFERER T, et al. Evaluation of the masked logic style mdpl on a prototype chip[C]//Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2007:81-94.

[125] MAISTRI P, TIRAN S, MAURINE P, et al. Countermeasures against em analysis for a secured fpga-based aes implementation[C]//Proceedings of the International Conference on Reconfigurable Computing and FPGAs.[S.l.]: IEEE, 2014:1-6.

[126] MESSERGES T S. Using second-order power analysis to attack dpa resistant software[C]//Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2000:238-251.

[127] ZHUANG Z, CHEN J, ZHANG H. A countermeasure for des with both rotating masks and secured s-boxes[C]//Proceedings of the Tenth International Conference on Computational Intelligence and Security.[S.l.]: IEEE, 2014:410-414.

[128] NASSAR M, SOUISSI Y, GUILLEY S, et al. Rsm: A small and fast countermeasure for aes, secure against 1st and 2nd-order zero-offset scas[C]//Proceedings of the Design, Automation & Test in Europe Conference & Exhibition.[S.l.]: IEEE, 2012:1173-1178.

[129] MIYAJAN A, SHI Z, HUANG C H, et al. An efficient high-order masking of aes using simd[C]//Proceedings of the Tenth International Conference on Computer Engineering & Systems.[S.l.]: IEEE, 2015:363-368.

[130] KIM H S, HONG S, LIM J. A fast and provably secure higher-order masking of aes s-box[C]//Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer Berlin Heidelberg, 2011:95-107.

[131] ELDIB H, WANG C, TAHA M, et al. Quantitative masking strength: Quantifying the power side-channel resistance of software code[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015,34（10）: 1558-1568.

[132] BRUGUIER F, BENOIT P, TORRES L, et al. Cost-effective design strategies for securing embedded processors[J]. IEEE Transactions on Emerging Topics in Computing, 2016,4（1）: 60-72.

[133] TIRI K, VERBAUWHEDE I. A vlsi design flow for secure side-channel attack resistant ics[C]//Proceedings of the Design, Automation and Test in Europe Conference and Exposition.[S.l.]: IEEE, 2005:58-63.

[134] REGAZZONI F, BADEL S, EISENBARTH T, et al. A simulation-based methodology for evaluating the dpa-resistance of cryptographic functional units with application to cmos and mcml technologies[C]//Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.[S.l.]: IEEE, 2007:209-214.

[135] NATALE G D, FLOTTES M L, ROUZEYRE B. An integrated validation environment for differential power analysis[C]//Proceedings of the IEEE International Symposium on Electronic Design, Test and Applications.[S.l.]: IEEE, 2008:527-532.

[136] BHASIN S, DANGER J L, GRABA T, et al. Physical security evaluation at an early design-phase: A side-channel aware simulation methodology[C]//Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems.[S.l.]: ACM, 2014:13.

[137] HE J, ZHAO Y, GUO X, et al. Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis[J]. IEEE Transactions on Very Large Scale Integration System（TVLSI）, 2017,25（10）: 2939-2948.

[138] LI H, MARKETTOS A T, MOORE S. Security evaluation against electromagnetic analysis at design time[C]//Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems.[S.l.]: Springer, 2005:280-292.